Time and space-multiplexed compilation challenges for dynamically reconfigurable processors

Takao Toi, Toru Awashima, Masato Motomura, Hideharu Amano

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

This paper presents our dynamically reconfigurable processor (DRP) and its compiler. We first introduce our DRP architecture, which is suitable for both parallelizable and control-intensive code segments since it has a stand-alone finite state machine that switches "contexts" consisting of many processing elements (PEs). Then, some optimization techniques used in the compiler are explained, such as a loop pipelining, iterative synthesis technique to shorten wire delay, and a technique to achieve higher area efficiency by utilizing the benefit of having multiple contexts. Lastly, two products are shown as application examples.

本文言語English
ホスト出版物のタイトル54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
DOI
出版ステータスPublished - 2011 10 13
イベント54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 - Seoul, Korea, Republic of
継続期間: 2011 8 72011 8 10

出版物シリーズ

名前Midwest Symposium on Circuits and Systems
ISSN(印刷版)1548-3746

Other

Other54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
国/地域Korea, Republic of
CitySeoul
Period11/8/711/8/10

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

フィンガープリント

「Time and space-multiplexed compilation challenges for dynamically reconfigurable processors」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル