Time-multiplexed execution on the dynamically reconfigurable processor - A performance/cost evaluation

Yohei Hasegawa; Shohei Abe; Katsuaki Deguchi; Masayasu Suzuki; Hideharu Amano

Time-multiplexed execution on the dynamically reconfigurable processor - A performance/cost evaluation

Yohei Hasegawa, Shohei Abe, Katsuaki Deguchi, Masayasu Suzuki, Hideharu Amano

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研究成果: Paper › 査読

抄録

Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. The impact of time-multiplexed execution to performance and cost is analyzed based on real designs including an IPsec router. The Parallelism Diagram which shows the required PEs in each step of the algorithm is introduced as the basis of the analysis, and models for performance and cost are shown. Evaluation results show that the time-multiplexed execution improves the performance per cost around 4.5 to 14 times than that of the case without time-multiplexed execution.

本文言語	English
ページ数	1
出版ステータス	Published - 2005 6 20
イベント	ACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005 - Monterey, CA, United States 継続期間: 2005 2 20 → 2005 2 22

Conference

Conference	ACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005
国/地域	United States
City	Monterey, CA
Period	05/2/20 → 05/2/22

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T1 - Time-multiplexed execution on the dynamically reconfigurable processor - A performance/cost evaluation

AU - Hasegawa, Yohei

AU - Abe, Shohei

AU - Deguchi, Katsuaki

AU - Suzuki, Masayasu

AU - Amano, Hideharu

PY - 2005/6/20

Y1 - 2005/6/20

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AB - Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. The impact of time-multiplexed execution to performance and cost is analyzed based on real designs including an IPsec router. The Parallelism Diagram which shows the required PEs in each step of the algorithm is introduced as the basis of the analysis, and models for performance and cost are shown. Evaluation results show that the time-multiplexed execution improves the performance per cost around 4.5 to 14 times than that of the case without time-multiplexed execution.

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Time-multiplexed execution on the dynamically reconfigurable processor - A performance/cost evaluation

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Conference

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