抄録
Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. The impact of time-multiplexed execution to performance and cost is analyzed based on real designs including an IPsec router. The Parallelism Diagram which shows the required PEs in each step of the algorithm is introduced as the basis of the analysis, and models for performance and cost are shown. Evaluation results show that the time-multiplexed execution improves the performance per cost around 4.5 to 14 times than that of the case without time-multiplexed execution.
| 元の言語 | English |
|---|---|
| ホスト出版物のタイトル | ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA |
| ページ | 265 |
| ページ数 | 1 |
| 出版物ステータス | Published - 2005 |
| イベント | ACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005 - Monterey, CA, United States 継続期間: 2005 2 20 → 2005 2 22 |
Other
| Other | ACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005 |
|---|---|
| 国 | United States |
| 市 | Monterey, CA |
| 期間 | 05/2/20 → 05/2/22 |
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ASJC Scopus subject areas
- Computer Science(all)
これを引用
Time-multiplexed execution on the dynamically reconfigurable processor - A performance/cost evaluation. / Hasegawa, Yohei; Abe, Shohei; Deguchi, Katsuaki; Suzuki, Masayasu; Amano, Hideharu.
ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA. 2005. p. 265.研究成果: Conference contribution
}
TY - GEN
T1 - Time-multiplexed execution on the dynamically reconfigurable processor - A performance/cost evaluation
AU - Hasegawa, Yohei
AU - Abe, Shohei
AU - Deguchi, Katsuaki
AU - Suzuki, Masayasu
AU - Amano, Hideharu
PY - 2005
Y1 - 2005
N2 - Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. The impact of time-multiplexed execution to performance and cost is analyzed based on real designs including an IPsec router. The Parallelism Diagram which shows the required PEs in each step of the algorithm is introduced as the basis of the analysis, and models for performance and cost are shown. Evaluation results show that the time-multiplexed execution improves the performance per cost around 4.5 to 14 times than that of the case without time-multiplexed execution.
AB - Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. The impact of time-multiplexed execution to performance and cost is analyzed based on real designs including an IPsec router. The Parallelism Diagram which shows the required PEs in each step of the algorithm is introduced as the basis of the analysis, and models for performance and cost are shown. Evaluation results show that the time-multiplexed execution improves the performance per cost around 4.5 to 14 times than that of the case without time-multiplexed execution.
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UR - http://www.scopus.com/inward/citedby.url?scp=20344393406&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:20344393406
SP - 265
BT - ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA
ER -