Time-multiplexed execution on the dynamically reconfigurable processor - A performance/cost evaluation

Yohei Hasegawa, Shohei Abe, Katsuaki Deguchi, Masayasu Suzuki, Hideharu Amano

研究成果: Conference contribution

抄録

Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. The impact of time-multiplexed execution to performance and cost is analyzed based on real designs including an IPsec router. The Parallelism Diagram which shows the required PEs in each step of the algorithm is introduced as the basis of the analysis, and models for performance and cost are shown. Evaluation results show that the time-multiplexed execution improves the performance per cost around 4.5 to 14 times than that of the case without time-multiplexed execution.

元の言語English
ホスト出版物のタイトルACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA
ページ265
ページ数1
出版物ステータスPublished - 2005
イベントACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005 - Monterey, CA, United States
継続期間: 2005 2 202005 2 22

Other

OtherACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005
United States
Monterey, CA
期間05/2/2005/2/22

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Costs
Routers
Electronic equipment
Networks (circuits)

ASJC Scopus subject areas

  • Computer Science(all)

これを引用

Hasegawa, Y., Abe, S., Deguchi, K., Suzuki, M., & Amano, H. (2005). Time-multiplexed execution on the dynamically reconfigurable processor - A performance/cost evaluation. : ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA (pp. 265)

Time-multiplexed execution on the dynamically reconfigurable processor - A performance/cost evaluation. / Hasegawa, Yohei; Abe, Shohei; Deguchi, Katsuaki; Suzuki, Masayasu; Amano, Hideharu.

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA. 2005. p. 265.

研究成果: Conference contribution

Hasegawa, Y, Abe, S, Deguchi, K, Suzuki, M & Amano, H 2005, Time-multiplexed execution on the dynamically reconfigurable processor - A performance/cost evaluation. : ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA. pp. 265, ACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005, Monterey, CA, United States, 05/2/20.
Hasegawa Y, Abe S, Deguchi K, Suzuki M, Amano H. Time-multiplexed execution on the dynamically reconfigurable processor - A performance/cost evaluation. : ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA. 2005. p. 265
Hasegawa, Yohei ; Abe, Shohei ; Deguchi, Katsuaki ; Suzuki, Masayasu ; Amano, Hideharu. / Time-multiplexed execution on the dynamically reconfigurable processor - A performance/cost evaluation. ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA. 2005. pp. 265
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