Top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme

Mototsugu Hamada, Masafumi Takahashi, Hideho Arakida, Akihiko Chiba, Toshihiro Terazawa, Takashi Ishikawa, Masahiro Kanazawa, Mutsunori Igarashi, Kimiyoshi Usami, Tadahiro Kuroda

研究成果: Conference article査読

82 被引用数 (Scopus)

抄録

A novel design technique which combines a Variable Supply-voltage scheme and a Clustered Voltage Scaling is presented (VS-CVS scheme). A theory to choose the optimum supply voltages in the VS-CVS scheme is discussed which enables us to perform chip design in a top-down fashion. Level-shifting flip-flops are developed which reduce power, delay, area penalties significantly. Application of this technique to an MPEG4 video codec saves 55% of the power dissipation without degrading circuit, performance compared to a conventional CMOS design.

本文言語English
ページ(範囲)495-498
ページ数4
ジャーナルProceedings of the Custom Integrated Circuits Conference
出版ステータスPublished - 1998 1 1
外部発表はい
イベントProceedings of the 1998 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA
継続期間: 1998 5 111998 5 14

ASJC Scopus subject areas

  • 電子工学および電気工学

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