TY - JOUR
T1 - Topological Channel Routing
AU - Haruyama, Shinichiro
AU - Wong, D. F.
AU - Fussell, Donald S.
PY - 1992/10
Y1 - 1992/10
N2 - A new approach to the two-layer channel routing problem is presented. The new two-layer channel router is designed to find solutions which minimize both wiring area and number of vias simultaneously. The method, called topological channel routing, analyzes the topological relationship of wires before the wires are mapped onto the channel. A unique layout design rule called an interleaving mesh is used. The interleaving mesh prohibits long wires on one layer from overlapping with wires on the other layer, and thus has smaller crosstalks of signals because of smaller capacitive couplings between those wires on different layers. Experimental results show that the algorithm generates very good solutions. For example, a height of 41 for the well-known Deutsch's Difficult Example without any parallel overlaps of wires has been obtained and simultaneously with a via count of 186, which is one of the best results ever reported in the literature.
AB - A new approach to the two-layer channel routing problem is presented. The new two-layer channel router is designed to find solutions which minimize both wiring area and number of vias simultaneously. The method, called topological channel routing, analyzes the topological relationship of wires before the wires are mapped onto the channel. A unique layout design rule called an interleaving mesh is used. The interleaving mesh prohibits long wires on one layer from overlapping with wires on the other layer, and thus has smaller crosstalks of signals because of smaller capacitive couplings between those wires on different layers. Experimental results show that the algorithm generates very good solutions. For example, a height of 41 for the well-known Deutsch's Difficult Example without any parallel overlaps of wires has been obtained and simultaneously with a via count of 186, which is one of the best results ever reported in the literature.
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U2 - 10.1109/43.170984
DO - 10.1109/43.170984
M3 - Article
AN - SCOPUS:0026929142
SN - 0278-0070
VL - 11
SP - 1177
EP - 1197
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 10
ER -