抄録
A high speed and scalable ATM switch architecture, the TORUS-switch, is proposed. The switch is an internal speed-up crosspoint switch with cylindrical configuration. The self-bit-synchronisation technique is adopted to achieve high speed cell transmission without requiring high-density implementation technology. Distributed contention control based on the fixed output-precedence scheme is adopted. This control is so simple that the control circuit is achieved with only one gate in each crosspoint. A TORUS-switch is fabricated as an ultrahigh speed crosspoint LSI using the advanced Si-bipolar process. Measured results confirm that the TORUS-switch can be used to realise an expandable terabit-rate ATM switch that is also efficient.
本文言語 | English |
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ページ(範囲) | 906-908 |
ページ数 | 3 |
ジャーナル | Electronics Letters |
巻 | 31 |
号 | 11 |
DOI | |
出版ステータス | Published - 1995 5月 25 |
外部発表 | はい |
ASJC Scopus subject areas
- 電子工学および電気工学