Trax Solver on Zynq using incremental update algorithm

Hiroshi Nakahara, Tetsui Ohkubo, Hideki Shimura, Ryotaro Sakai, Chiharu Tsuruta, Takahiro Kaneda, Hideharu Amano

研究成果: Conference contribution

抄録

This paper proposes a software/hardware co-design system for a Trax solver. Since development with Hardware Description Language (HDL) is tough work, we selected an approach: 1. writing C++ code, 2. finding bottleneck of the problem, and 3. re-writing the bottleneck part in the High Level Synthesis(HLS). Generally, game AI algorithm is divided into 3 parts, data structure, searching, and board evaluation. In this design, we focused on the data structure and implemented an incremental update algorithm. As a result, we can detect a line and an attack with O(1). Also, we implemented a local pruning, which reduces search area when the search depth becomes large in alpha beta tree search. The implemented solver works with 150MHz clock on Xilinx XC7Z020-CLG484 of Digilent ZedBoard.

本文言語English
ホスト出版物のタイトルProceedings of the 2016 International Conference on Field-Programmable Technology, FPT 2016
出版社Institute of Electrical and Electronics Engineers Inc.
ページ323-326
ページ数4
ISBN(電子版)9781509056026
DOI
出版ステータスPublished - 2017 5 15
イベント15th International Conference on Field-Programmable Technology, FPT 2016 - Xi'an, China
継続期間: 2016 12 72016 12 9

Other

Other15th International Conference on Field-Programmable Technology, FPT 2016
国/地域China
CityXi'an
Period16/12/716/12/9

ASJC Scopus subject areas

  • コンピュータ ネットワークおよび通信
  • 電子工学および電気工学
  • 安全性、リスク、信頼性、品質管理
  • 器械工学
  • ハードウェアとアーキテクチャ

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