抄録
A software/hardware co-design system for a Trax solver is proposed. Implementation of Trax AI is challenging due to its complicated rules, so we adopted an embedded system called Zynq (Zynq-7000 AP SoC) and introduced a High Level Synthesis (HLS) design. We also added Deep Q-Network, a machine learning algorithm, to the system for use as an evaluation function. Our solver automatically optimizes its own evaluation function through games with humans or other AIs. The implemented solver works with a 150-MHz clock on the Xilinx XC7Z020-CLG484 of a Digilent ZedBoard. A part of the Deep Q-Network job can be executed on the FPGA of the Zynq board more than 26 times faster than with ARM Coretex-A9 650-MHz software.
本文言語 | English |
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ホスト出版物のタイトル | 2015 International Conference on Field Programmable Technology, FPT 2015 |
出版社 | Institute of Electrical and Electronics Engineers Inc. |
ページ | 272-275 |
ページ数 | 4 |
ISBN(印刷版) | 9781467390910 |
DOI | |
出版ステータス | Published - 2016 1月 25 |
イベント | International Conference on Field Programmable Technology, FPT 2015 - Queenstown, New Zealand 継続期間: 2015 12月 7 → 2015 12月 9 |
Other
Other | International Conference on Field Programmable Technology, FPT 2015 |
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国/地域 | New Zealand |
City | Queenstown |
Period | 15/12/7 → 15/12/9 |
ASJC Scopus subject areas
- コンピュータ サイエンスの応用
- ハードウェアとアーキテクチャ
- ソフトウェア