Unified understanding of Vth and Id variability in tri-gate nanowire MOSFETs

M. Saitoh, K. Ota, C. Tanaka, Y. Nakabayashi, K. Uchida, T. Numata

    研究成果: Conference contribution

    2 被引用数 (Scopus)

    抄録

    We present the systematic study of Vth and Idlin/ Idsat variability of nanowire transistors (NW Tr.) with various parameters (NW width (WNW) and height (HNW) down to 10nm, NW number (NNW), NW directions, channel dopants). By adopting NW circumference as Weff, the universal line appears in Pelgrom plot of both σVth and σId for a wide range of gate length (Lg), WNW and HNW. We found A vt reduction in NW Tr. compared to planar SOI Tr. due to gate grain alignment. Deviation of σVth and σIdlin of the narrowest Tr. from the universal line was eliminated by suppressing the parasitic resistance (RSD). σIdsat and σI dlin in NW Tr. can be reduced by improving the surface-roughness- limited mobility and its variations, respectively.

    本文言語English
    ホスト出版物のタイトル2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers
    ページ132-133
    ページ数2
    出版ステータスPublished - 2011 9 16
    イベント2011 Symposium on VLSI Circuits, VLSIC 2011 - Kyoto, Japan
    継続期間: 2011 6 152011 6 17

    出版物シリーズ

    名前IEEE Symposium on VLSI Circuits, Digest of Technical Papers

    Other

    Other2011 Symposium on VLSI Circuits, VLSIC 2011
    国/地域Japan
    CityKyoto
    Period11/6/1511/6/17

    ASJC Scopus subject areas

    • 電子材料、光学材料、および磁性材料
    • 電子工学および電気工学

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