Utilizing surplus timing for power reduction

Mototsugu Hamada, Yukio Ootaguro, Tadahiro Kuroda

    研究成果: Article

    60 引用 (Scopus)

    抜粋

    Multiple Vdd's, multiple Vth's, and multiple transistor width for utilizing surplus timing in non-critical paths for power reduction is investigated. Theoretical models are developed from which rules of thumb for optimum Vdd's, Vth's, and W's are derived, as well as knowledge for future design.

    元の言語English
    ページ(範囲)89-92
    ページ数4
    ジャーナルProceedings of the Custom Integrated Circuits Conference
    DOI
    出版物ステータスPublished - 2001 1 1

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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