TY - JOUR

T1 - VCO-Based Comparator

T2 - A Fully Adaptive Noise Scaling Comparator for High-Precision and Low-Power SAR ADCs

AU - Yoshioka, Kentaro

N1 - Publisher Copyright:
© 1993-2012 IEEE.

PY - 2021/12/1

Y1 - 2021/12/1

N2 - A voltage-controlled oscillator (VCO)-based comparator that automatically adapts its noise performance reflecting the input voltage difference ( $\Delta V_{\text {in}}$ ) is presented. Such adaptive operation significantly reduces the power of high-precision comparators in successive-approximation-register (SAR) ADCs. $\Delta V_{\text {in}}$ is integrated as a time difference via the VCO, where the integration continues as long as the time difference is below a certain threshold, defined by the phase detector deadzone. Thus, when $\Delta V_{\text {in}}$ is large, the comparator operates as a low-power delay line-based comparator, and with small $\Delta V_{\text {in}}$ , the VCO oscillates to integrate the input signal and suppresses the comparator noise. The required oscillations to complete the comparison are inversely proportional to $\Delta V_{\text {in}}$ , realizing fully adaptive noise and power scaling. This article provides a detailed analysis and specific design guidelines of the VCO comparator. Moreover, the PVT drift tolerance and detailed circuit implementations are deeply discussed as well. For proof-of-concept, a 13-bit SAR ADC with the proposed VCO-based comparator was fabricated in 65-nm CMOS. By off-chip LMS calibration, the ADC achieves peak SNDR 66 dB at 1 MS/s with a peak FoM of 29 fJ/conv.-step.

AB - A voltage-controlled oscillator (VCO)-based comparator that automatically adapts its noise performance reflecting the input voltage difference ( $\Delta V_{\text {in}}$ ) is presented. Such adaptive operation significantly reduces the power of high-precision comparators in successive-approximation-register (SAR) ADCs. $\Delta V_{\text {in}}$ is integrated as a time difference via the VCO, where the integration continues as long as the time difference is below a certain threshold, defined by the phase detector deadzone. Thus, when $\Delta V_{\text {in}}$ is large, the comparator operates as a low-power delay line-based comparator, and with small $\Delta V_{\text {in}}$ , the VCO oscillates to integrate the input signal and suppresses the comparator noise. The required oscillations to complete the comparison are inversely proportional to $\Delta V_{\text {in}}$ , realizing fully adaptive noise and power scaling. This article provides a detailed analysis and specific design guidelines of the VCO comparator. Moreover, the PVT drift tolerance and detailed circuit implementations are deeply discussed as well. For proof-of-concept, a 13-bit SAR ADC with the proposed VCO-based comparator was fabricated in 65-nm CMOS. By off-chip LMS calibration, the ADC achieves peak SNDR 66 dB at 1 MS/s with a peak FoM of 29 fJ/conv.-step.

KW - Eye-opening operation

KW - low-power comparator

KW - successive-approximation-register (SAR) ADC

KW - voltage-controlled oscillator (VCO)-comparator

UR - http://www.scopus.com/inward/record.url?scp=85118586378&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85118586378&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2021.3119691

DO - 10.1109/TVLSI.2021.3119691

M3 - Article

AN - SCOPUS:85118586378

VL - 29

SP - 2143

EP - 2152

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 12

ER -