Virtual core based synthesis of SoC architectures

Hiroaki Nishi, Michiaki Muraoka, Rafael K. Morizawa, Hideaki Yokota, Hideyuki Hamada

研究成果: Conference contribution

抄録

The reuse of high-level design intellectual properties is indispensable to reduce SoC design time. It has been difficult for SoC designers to design and compare two or more SoC architectures in a given product design time. In this paper, we present a synthesis methodology of SoC architectures using Virtual Cores (VCores) to perform architectural explorations in a short period. The proposed synthesis methodology generates an initial architecture, which consists of a CPU, buses, I/Os. etc., and makes tradeoffs between hardware and software on mapped software VCores and hardware VCores models. The authors show the usefulness of me proposed method from the results of an architecture level design experiment.

本文言語English
ホスト出版物のタイトルASICON 2003 - 2003 5th International Conference on ASIC, Proceedings
編集者Ting-Ao Tang, Wenhong Li, Huihua Yu
出版社Institute of Electrical and Electronics Engineers Inc.
ページ35-40
ページ数6
ISBN(電子版)078037889X
DOI
出版ステータスPublished - 2003
外部発表はい
イベント5th International Conference on ASIC, ASICON 2003 - Beijing, China
継続期間: 2003 10 212003 10 24

出版物シリーズ

名前IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings
1
ISSN(印刷版)1523-553X

Conference

Conference5th International Conference on ASIC, ASICON 2003
国/地域China
CityBeijing
Period03/10/2103/10/24

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 工学(全般)
  • 産業および生産工学
  • 電子工学および電気工学

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