VIX: A router architecture for priority-aware networks-on-chip

Takuma Kogo, Nobuyuki Yamasaki

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

In future many-core chip multiprocessors (CMPs) and systems-on-chips (SoCs) architectures, networks-on-chip (NoC) will be one of the most critical components. In CMPs and SoCs, multiple applications will be executed concurrently and they interfere each other. Thus, packet conflicts will be caused in the NoC. Priority control is required in such environments, because each application has different bandwidth requirements and causes different traffic patterns of the packets. Unfortunately priority control degrades network performance and significantly increases the area of a priority-aware on-chip router. This paper proposes a router architecture for priority-aware NoCs in order to mitigate the performance and area overheads due to the priority control. We implement the proposed router architecture using a 90nm process technology. The synthesis result shows no critical path overhead and drastic reduction of the router area. The simulation result on a 8-ary 2-mesh network shows that the average latency of higher priority packets is reduced at the near saturation point.

本文言語English
ホスト出版物のタイトルProceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2010
出版社IEEE Computer Society
ページ11-18
ページ数8
ISBN(印刷版)9780769543963
DOI
出版ステータスPublished - 2010
イベント2010 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2010 - Hilo, HI, United States
継続期間: 2010 1月 172010 1月 19

出版物シリーズ

名前Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems
ISSN(印刷版)1537-3223

Other

Other2010 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2010
国/地域United States
CityHilo, HI
Period10/1/1710/1/19

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ

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