In future many-core chip multiprocessors (CMPs) and systems-on-chips (SoCs) architectures, networks-on-chip (NoC) will be one of the most critical components. In CMPs and SoCs, multiple applications will be executed concurrently and they interfere each other. Thus, packet conflicts will be caused in the NoC. Priority control is required in such environments, because each application has different bandwidth requirements and causes different traffic patterns of the packets. Unfortunately priority control degrades network performance and significantly increases the area of a priority-aware on-chip router. This paper proposes a router architecture for priority-aware NoCs in order to mitigate the performance and area overheads due to the priority control. We implement the proposed router architecture using a 90nm process technology. The synthesis result shows no critical path overhead and drastic reduction of the router area. The simulation result on a 8-ary 2-mesh network shows that the average latency of higher priority packets is reduced at the near saturation point.