Through the use of an extended field programmable gate array (FPGA) technology, a large digital circuit can be realized on a relatively small amount of real hardware. Several configuration RAM modules are provided inside the FPGA chip, and the configuration of the gate array can be rapidly changed by replacing the active module. Data for configuration are transferred from an off-chip backup RAM to an unused configuration RAM module. A novel computation mechanism called the WASMII, which executes a target dataflow graph directly, can be proposed on the basis of this "virtual hardware." A WASMII chip consists of the FPGA for virtual hardware and an additional mechanism to replace configuration RAM modules in a data-driven manner. Configuration data are preloaded in the order assigned in advance by a static scheduling preprocessor. By connecting a number of WASMII chips, a highly parallel system can be easily constructed.
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