Wire congestion aware synthesis for a dynamically reconfigurable processor

Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, Hideharu Amano

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

This paper presents two iterative synthesis techniques between a high-level synthesizer (HLS) and the place and route tool to shorten the prolonged wire delay for a dynamically reconfigurable processor. At first, we use feedback wire delays for each context to a scheduler in the HLS. The experimental results showed that a critical-path delay was shorten 21% on average for applications with timing closure problems. Second, we skip the routing and estimate wire delays based on their congestions. The synthesis time was cut by 1/3 with only four points down on delay improvement rate.

本文言語English
ホスト出版物のタイトルProceedings - 2010 International Conference on Field-Programmable Technology, FPT'10
ページ300-303
ページ数4
DOI
出版ステータスPublished - 2010 12月 1
イベント2010 International Conference on Field-Programmable Technology, FPT'10 - Beijing, China
継続期間: 2010 12月 82010 12月 10

出版物シリーズ

名前Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10

Other

Other2010 International Conference on Field-Programmable Technology, FPT'10
国/地域China
CityBeijing
Period10/12/810/12/10

ASJC Scopus subject areas

  • 計算理論と計算数学
  • コンピュータ サイエンスの応用

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