Wire-speed implementation of sliding-window aggregate operator over out-of-order data streams

Yasin Oge, Masato Yoshimi, Takefumi Miyoshi, Hideyuki Kawashima, Hidetsugu Irie, Tsutomu Yoshinaga

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

This paper shows the design and evaluation of an FPGA-based accelerator for sliding-window aggregation over data streams with out-of-order data arrival. We propose an order-agnostic hardware implementation technique for windowing operators based on a one-pass query evaluation strategy called Window-ID, which is originally proposed for software implementation. The proposed implementation succeeds to process out-of-order data items, or tuples, at wire speed due to the simultaneous evaluations of overlapping sliding-windows. In order to verify the effectiveness of the proposed approach, we have also implemented an experimental system as a case study. Our experiments demonstrate that the proposed accelerator with a network interface achieves an effective throughput around 760 Mbps or equivalently nearly 6 million tuples per second, by fully utilizing the available bandwidth of the network interface.

本文言語English
ホスト出版物のタイトルProceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013
出版社IEEE Computer Society
ページ55-60
ページ数6
ISBN(印刷版)9780768550862
DOI
出版ステータスPublished - 2013 1 1
外部発表はい
イベント2013 IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013 - Tokyo, Japan
継続期間: 2013 9 262013 9 28

出版物シリーズ

名前Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013

Other

Other2013 IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013
CountryJapan
CityTokyo
Period13/9/2613/9/28

ASJC Scopus subject areas

  • Hardware and Architecture

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